Enigma VHDL

A gate-level Enigma cipher machine in VHDL. Automated testing uncovered two bugs that had been hidden for nine years, both now fixed and pinned down by 241 exhaustive checks.
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Boolean equations derived from truth tables, simplified with Karnaugh maps and mapped onto AND, OR and NOT gates and T flip-flops. No behavioural shortcuts, which is slower to write and much easier to get wrong, and that is exactly the point of doing it that way.
This is also where Motorola 68K assembly and computer architecture live. I picked all of it up studying Electronic Engineering at the UPV/EHU, a degree I did not finish, and it still changes how I read code several abstraction levels above it.
The Enigma below is the piece I keep coming back to. It is a working cipher machine at gate level, and it is also the clearest example I have of why a design you understand well is not a design you have verified.

A gate-level Enigma cipher machine in VHDL. Automated testing uncovered two bugs that had been hidden for nine years, both now fixed and pinned down by 241 exhaustive checks.
Read more...
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